Testing signal development on a bit line in an sram

ABSTRACT

An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.

This application is a divisional of prior application Ser. No.13/611,863, filed Sep. 12, 2012, now U.S. Pat. No. 9,001,568, grantedApr. 7, 2015.

BACKGROUND

This invention relates to integrated circuits, particularly to staticrandom access memory (SRAM) devices, in either embedded form or standalone (i.e. discrete) form.

Memory cells in SRAM devices store logical binary values (i.e. either alogical one or a logical zero). When a memory cell is selected by a wordline during a read, the voltage on a latch in the memory cell begins tochange the voltages on the bit lines attached to the memory cell (i.e.signal is developing on the bit lines). Because the signal on the bitlines is initially small, a certain amount of time must pass to allowthe signal on the bit lines to grow larger. When the signal on the bitlines reaches a certain value, this value may be sensed by a sense amp.The sense amp increases the voltage found on the bit lines so that thesignal may be transferred to another part of the SRAM.

When data is read from an SRAM memory cell and the time allowed for thesignal on the bit lines to increase is too short, the sense amp may failto amplify the correct logical value and an error occurs in the SRAM.When data is read from an SRAM memory cell and the time allowed for thesignal on the bit lines to increase is too long, the sense amp properlyamplifies the correct logical value. However, because the time allowedwas long, the read access time of the SRAM increases. In order to keepthe read access time as short as possible and read correct data, it isimportant to be able to vary the amount of time allowed for the signalon the bit lines to develop. Further, it is important to test SRAMs toensure the availability of sufficient read margin by varying the amountof time allowed for a signal to develop on the bit lines during a readof an SRAM memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an SRAM (Static Random Access Memory).(Prior Art)

FIG. 2 is a timing diagram illustrating signal development time. (PriorArt)

FIG. 3 is a block diagram of signal delay circuit. (Prior Art)

FIG. 4 is block diagram of a circuit that is used to determine thesignal develop time of a memory cell. (Prior Art)

FIG. 5 is block diagram of a circuit used to determine the signaldevelop time of a memory cell in an SRAM according to an embodiment ofthe invention.

FIG. 6 is a flow chart illustrating a method of measuring the signaldevelopment time of an array of SRAM cells according to an embodiment ofthe invention.

DETAILED DESCRIPTION

The drawings and description, in general, disclose a method and anelectrical device for determining the signal development time of amemory cell in an SRAM. In an embodiment of the invention, a fixednumber of dummy memory cells on a dummy word line are selected to drivea pair of dummy bit lines when the dummy word line is selected. Thefixed number of dummy memory cells each contains the same binary logicalvalue (e.g. a logical one). After the number of fixed number of dummymemory cells have been selected, a binary logical value is written to amemory cell in the SRAM.

Next the dummy word line that is electrically connected to the selecteddummy memory cell and the word line that is electrically connected tothe memory cell that was written to with binary logical value, aredriven to logical high values. When the dummy word line is driven to alogical high value, the selected dummy memory cells drive the dummy bitlines. When the word line is driven to a logical high value, theselected memory cell in the SRAM drives the bit lines. One of the dummybit lines drives a buffer that in turn enables the sense ampelectrically connected to the bit lines to amplify the voltagedifferential on the bit lines.

The signal on the bit lines is allowed to increase until the sense ampis enabled. The time allowed for the signal on the bit lines to bedeveloped is determined by the delay from the dummy word line going to alogical high value to the time the sense amp is enabled. When the delayis too short, the sense amp will be enabled too early and the correctdigital logical value may not be amplified. When the delay is too long,the sense amp will be enabled later than is necessary and the read timeof the memory cell will increase.

The time allowed for the signal on the bit lines to be developed may beincreased or decreased by changing the number of dummy memory cells thatdrives the dummy bit lines. For example, the time allowed for the signalon the bit lines to be developed may be decreased by increasing thenumber of dummy memory cells that drive the dummy bit lines. In anotherexample, the time allowed for the signal on the bit lines to bedeveloped may be increased by decreasing the number of dummy memorycells that drive the dummy bit lines. By varying the time allowed forsignal to develop on the bit lines, a trade-off between access time andread margin is achieved.

FIG. 1 is a block diagram of an SRAM (Static Random Access Memory) 100(Prior Art). In this embodiment only a single array of SRAM cells 104 isshown for illustrative purposes. Typically, an SRAM has more than onearray of SRAM cells. In this example, a pre-charge circuit 102pre-charges the bit lines 147 in the memory cell array 104 to apredetermined voltage before the memory cell array 104 is either readfrom or written to.

When the memory cell array 104 is read from, an address 144 is input tothe address registers 118. The address 144 stored in the addressregisters 118 is then clocked by a clock signal CK from the addressregisters to a row decoder 114 and a column decoder 116. In thisexample, the row decoder 114 drives a word line 157 in the memory cellarray 104 to a logical high value. Memory cells attached to the selectedword line provide data that is passed through the pre-charge circuit 102and the write circuit 106 to the column select circuit 108. The columnselect circuit 108 selects what data 130 is provided to the senseamplifiers 110 based on the output 154 of the column decoder 116. Thesense amplifiers 110 increase the voltage of the selected data 130 whenthe sense amplifiers are enabled by signal SA_E. The amplified signals132 are sent to the output buffers 112. The output buffers 112 retainthe amplified signals 132. When the output enable signal 142 is active,the output buffers 112 send the stored data 146 in the output buffers112 from the SRAM 100 to other circuits.

When the memory cell array 104 is written to, an address 144 is input tothe address registers 118 and the write enable signal 148 is activated.The address 144 stored in the address registers 118 is then clocked by aclock signal CK from the address registers to a row decoder 114 and acolumn decoder 116. In this example, the row decoder 114 drives a wordline 157 in the memory cell array 104 to a logical high value. Theselected word line 157 along with the selected bit lines determine whichmemory cells in the memory cell array 104 will be written to. The inputenable signal IE allows data 136 previously stored in the inputregisters 120 to be written into the memory cell array 104.

FIG. 2 is a timing diagram illustrating signal development time. Thesignal develop time t_(sd) in this example is equal to the time measuredfrom when the word line 157 is approximately 0.5*VDD to the time whenthe sense amp enable signal SA_E is approximately 0.5*VDD. The signaldevelop time may be implemented using delay blocks as shown in FIG. 3.In this example of signal delay circuit, the word line signal 157 isinput to a delay block 302. Delay block 302 in this example consists oftwo inverters INV1 and INV2 in series. However, other types of circuitsmay be used to implement a delay block. The output of delay block 302 isinput to delay block 304. The output of delay block 304 is input ofanother delay block not shown. The last two delay blocks of the signaldelay circuit are 306 and 308. The number of delay blocks used isdetermined by the delay time needed.

During design of an SRAM, the signal development time is determinedusing models that estimate how much time is needed for a signal todevelop on bit lines and have a sense amp accurately amplify the signal.However, because circuits do not always function as predicted by models,testing is needed to ensure that the time allowed is sufficient tocorrectly amplify the signal.

After SRAMs have been fabricated and before they are shipped to acustomer, SRAMs are tested to insure that they function properly. Toinsure that an SRAM is functioning properly and to provide additionalmargin, the SRAM is tested with signal development time that is lessthan what the customer will use. This will ensure that SRAM bits that donot have sufficient margin with respect to customer use will beidentified during testing. FIG. 4 is block diagram of a circuit that isused to vary the signal develop time of a memory cell.

FIG. 4 includes 8 dummy rows DR1-DR8. Each of these rows includes 128dummy memory cells, DCM. The dummy memory cells are identical to anormal SRAM memory cell except these memory cells are “hard-wired” to alogical one or a logical zero value. A memory cell is hard-wired whenthe binary logical value stored in it is static and cannot be writtento. These dummy memory cells are not used to retain actual data but areused to create loads for dummy word lines DWL1-DWL8 and to drive dummybit lines DBL1 and DBL2. In this example, dummy bit line DBL1 isconnected to an inverter INV1 that drives a sense amp enable block 402.In other embodiments of the invention either a non-inverting buffer oran inverting buffer may be used depending on the logical value on DBL1.The sense amp enable block 402 determines which signal is used to enablea selected sense amp.

FIG. 4 also includes 128 rows R1-R128. Each of these rows includes 1dummy memory cell DCM and 128 memory cells. Word lines WL1-WL128 areelectrically connected to the memory cells in their respectively rowsR1-R128. However, the word lines are not directly electrically connectedto the dummy memory cell DMC in their respective rows R1-R128. Thesingle dummy memory cell is identical to a normal SRAM memory cellexcept that it is “hard-wired” to a logical one or a logical zero value.The single dummy memory cell is not used to retain actual data but isused to create loads for dummy bit lines DBL1-DBL2. The memory cells MCin rows R1-128 retain actual data. In this example, bit lines pairsBLP1-BLP128 are electrically connected to memory cells MC and sense ampsSA in their respective columns C1-C128.

During normal operation (i.e. not being tested), any combination ofdummy word lines DWL1-DWL8 is driven to high logical value and one wordline, for example WL3, from word lines WL1-WL128 is selected by drivingthe word line WL3 to a logical high value. When WL3 is driven to alogical high value, memory cells MC contained in R3 are activated (dummymemory cell MC however is not activated) and bit line pairs BP1-BP128are actively driven by the memory cell in its respective column C1-C128.In this example, a bit decoder (not shown) determines how many bits aresensed by sense amp SA in their columns C1-C128 and then driven to othercircuit in the SRAM. During normal operation, the dummy sense enablesignal DSA_E may be used to control the time that a signal is developedon the bit lines of a memory cell or a timed sense amp enable TSA_E thatuses a signal delay circuit 300 (see FIG. 3) may be used to control thetime that a signal is developed on the bit lines of a memory cell. Thesense amp enable block 402 determines whether sense enable signal DSA_Eor TSA_E is used during normal operation.

During normal operation, the time allowed for signal development can bevaried by selecting one or more of the eight dummy memory cells D1-D8electrically connected to the dummy bit lines DBL1 and DBL2. Forexample, when only a relatively slow access time is required, only oneor two dummy memory cells are selected from the eight dummy memory cellsD1-D8 by selecting two dummy word lines concurrently from the eightdummy word lines DL1-DWL8. However, when a relatively faster access timeis required, six or more dummy memory cells are selected from the eightdummy memory cells D1-D8 by selecting six dummy word lines concurrentlyfrom the eight dummy word lines DL1-DWL8. The signal delay circuit 300may also be used during normal operation but the signal development inthis case is fixed by the signal delay circuit 300.

During operation of a signal development test, one or more dummy wordlines DWL1-DWL8 are driven to a logical high level and one word line,for example WL3, from word lines WL1-WL128 is selected by driving theword line WL3 to a logical high value. The number of dummy word linesselected depends on how fast dummy bit lines DBL1 and DBL2 need to bedriven. For example, only one dummy word line is driven when the dummybit lines need to be driven relatively slowly. However, when dummy bitlines DBL1 and DBL2 need to be driven relatively fast, 6 or more dummyword lines are activated at the same time for example. In thisembodiment of the invention, the most extreme screening of the accesstime of a memory cell in the SRAM takes place when all eight of thedummy memory cells D1-D8 are activated concurrently. All eight of thedummy memory cells D1-D8 are activated concurrently when all eight dummyword lines are driven to a logical high value concurrently.

As previously discussed, the dummy rows DR1-DR8 and the dummy bit linesDBL1 and DBL2 are added to test the signal development time of memorycells MC in an SRAM and to vary the time allowed for signal developmentduring normal operation of the SRAM. None of the dummy memory cells DMCstore actual data. Each dummy row DR1-DR8 has 128 dummy memory cells inorder to create a load that is very similar to the load seen by a wordline in one of the rows R1-R128. Only one dummy cell (i.e. D1-D8) ineach dummy row DR1-DR8 drives the dummy bit lines DBL1 and BDBL2. Morethan one dummy row is used in order to be able to drive the dummy bitlines DBL1 and DBL2 faster. The dummy rows DR1-DR8 use area on anintegrated circuit that contains an SRAM. An embodiment of the inventionwill now be described that reduces the number of dummy rows required totest signal development and to vary the signal development time duringnormal operation.

FIG. 5 is block diagram of a circuit used to test the signal developtime of a memory cell and to vary the signal development time duringnormal operation of an SRAM according to an embodiment of the invention.FIG. 5 includes 1 dummy row DR1. The dummy row DR1 includes 128 dummymemory cells, DCM. The dummy memory cells are identical to a normal SRAMmemory cell except these memory cells are “hard-wired” to a logical oneor a logical zero value. A memory cell is hard-wired when the binarylogical value stored in it is static and cannot be written to. Thesedummy memory cells are not used to retain actual data but are used tocreate a load for dummy word line DWL1 and to drive dummy bit lines DBL1and DBL2. In this example, dummy bit line DBL1 is connected to aninverter INV1 that drives a sense amp enable block 502. In otherembodiments of the invention either a non-inverting buffer or aninverting buffer may be used depending on the logical value on DBL1. Thesense amp enable block 502 determines which signal is used to enable aselected sense amp.

The number of dummy memory cells used to drive the dummy bit lines DBL1and DBL2 may be selected by logic block 502. In this embodiment of theinvention, a multi-bit signal 504 is input to the logic block 502. Basedon the multi-bit signal 504, the outputs 506, 508 and 510 of the logicblock 502 activates combinations of switches 520, 522 and 524 to allow1, 2, 3 or 4 dummy memory cells to be selected from dummy memory cells512, 514, 516 and 518. The dummy bit lines DBL1 and DBL2 are driven theslowest when only dummy memory cell 512 drives them. The dummy bit linesDBL1 and DBL2 are driven the fastest when dummy memory cells 512, 514,516 and 518 drive them concurrently.

FIG. 5 also includes 128 rows R1-R128. Each of these rows includes 1dummy memory cell DCM and 128 memory cells. Word lines WL1-WL128 areelectrically connected to the memory cells in their respectively rowsR1-R128. The single dummy memory cell is not used to retain actual databut is used to create loads for dummy bit lines DBL1-DBL2. The memorycells MC in rows R1-128 retain actual data. In this example, bit linespairs BLP1-BLP128 are electrically connected to memory cells MC andsense amps SA in their respective columns C1-C128.

During normal operation, the time allowed for signal development can bevaried by selecting one or more of the four dummy memory cells 512, 514,516 and 518 electrically connected to the dummy bit lines DBL1 and DBL2and the dummy word line DWL1. For example, when only a relatively slowaccess time is required, only one dummy memory cell is selected from thefour dummy memory cells 512, 514, 516 and 518 by selecting the dummyword line DL1 and having the logic block 526 not select dummy memorycells 514, 516 and 518. However, when a relatively fast access time isrequired, all four dummy memory cells 512, 514, 516 and 518 are selectedby selecting the dummy word line DWL1 and having the logic block 526select dummy memory cells 514, 516 and 518. The signal delay circuit 300may also be used during normal operation but the signal development inthis case is fixed by the signal delay circuit 300.

During operation of a signal development test, the dummy word line DWL1is driven to a logical high level and one word line, for example WL3,from word lines WL1-WL128 is selected by driving the word line WL3 to alogical high value. The number of dummy memory cells 512, 514, 516 and518 determines how fast dummy bit lines DBL1 and DBL2 can to be driven.For example, only one dummy memory cell 512 is used when the dummy bitlines need to be driven relatively slowly. However, when dummy bit linesDBL1 and DBL2 need to be driven relatively fast, all four dummy memorycells 512, 514, 516 and 518 are used. In this embodiment of theinvention, the most extreme screening of the access time of a memorycell in the SRAM takes place when all four of the dummy memory 512, 514,516 and 518 are used. All four of the dummy memory cells 512, 514, 516and 518 are activated by the logic block 526 when the multi-input signal504 indicates that all four dummy memory cells should be selected.

As previously discussed, the dummy row DR1 and the dummy bit lines DBL1and DBL2 are added to test the signal development time of memory cellsMC in an SRAM and to vary the time allowed for signal development duringnormal operation of the SRAM. None of the dummy memory cells DMC storeactual data. The dummy row DR1 has 128 dummy memory cells in order tocreate a load that is very similar to the load seen by a word line inone of the rows R1-R128. More than one dummy memory cell 512, 514, 516and 518 is used in order to be able to drive the dummy bit lines DBL1and DBL2 faster. Having a single dummy row DR1 instead of eight dummyrow D1-D8 (see FIG. 4) reduces the amount area needed on an integratedcircuit that contains an SRAM.

In another embodiment (not shown), two dummy rows may be used instead ofone due to design constraints on the layout of memory cells. Often asingle memory cell cannot be laid out as a single unit. As a result,four memory cells may be used to compose a repeatable memory unit. Whenthis is the case, two dummy rows would be used. However, the sameprinciples explained in the previous embodiment would be applied.

FIG. 6 is a flow chart illustrating a method of testing the signaldevelopment time of a memory cell in an SRAM as well as a method ofselecting the signal development time during normal operation of an SRAMaccording to an embodiment of the invention. During step 602, the numberof dummy memory cells DMC selected from the plurality of dummy memorycells electrically connected to the single dummy word line DLW1 to drivethe dummy bit lines DBL1 and DBL2 is selected. In this example,combinations of dummy memory cells 512, 514, 516 and 518 may be selectedto drive the dummy bit lines DBL1 and DBL2. However, the dummy word lineDWL1 may be configured to allow the selection of more or fewer dummymemory cells DMC in other embodiments of the invention. During step 604a first binary logical value is written to a memory cell in the SRAM.After the first binary logical value is written to the memory cell inthe SRAM, a logical high value is applied to the word line connected tothe memory cell and to the single dummy word line DWL1 concurrently asdescribed in step 606. Next the second binary logical value on the firstdummy bit line DBL1 is applied to an input of a buffer as shown in step608. The output of the buffer enables a sense amp to electricallyconnect to the selected memory cell in the SRAM as shown in step 610.

The foregoing description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form disclosed, and othermodifications and variations may be possible in light of the aboveteachings. The embodiments were chosen and described in order to bestexplain the applicable principles and their practical application tothereby enable others skilled in the art to best utilize variousembodiments and various modifications as are suited to the particularuse contemplated. It is intended that the appended claims be construedto include other alternative embodiments except insofar as limited bythe prior art.

What is claimed is:
 1. An electronic device for testing the signaldevelopment time of a selected memory cell in a static random accessmemory (SRAM) comprising: a single dummy word line wherein a firstplurality of dummy memory cells are electrically connected to the singledummy word line; a dummy bit line pair comprising a first dummy bit lineand a second dummy bit line wherein a second plurality of dummy memorycells is connected to the dummy bit line pair; a buffer having at leastone input and at least one output; wherein the at least one input iselectrically connected to one of the dummy bit lines; wherein the outputof the buffer is electrically connected to a sense amp electricallyconnected to the selected memory cell; wherein a number of dummy memorycells from the first plurality of dummy cells electrically drive thedummy bit line pair when the dummy word line is driven to a logical highvalue; wherein a word line that is electrically connected to theselected memory cell is driven to a logical high value concurrently withthe single dummy word line being driven to a logical high value.
 2. Theelectronic device of claim 1 wherein the number of dummy memory cellsfrom the first plurality of dummy cells is determined by a logicalblock.
 3. An electronic device for selecting the amount of time forsignal development in a static random access memory (SRAM) comprising: asingle dummy word line wherein a first plurality of dummy memory cellsare electrically connected to the single dummy word line; a dummy bitline pair comprising a first dummy bit line and a second dummy bit linewherein a second plurality of dummy memory cells is connected to thedummy bit line pair; a buffer having at least one input and at least oneoutput; wherein the at least one input is electrically connected to oneof the dummy bit lines; wherein the output of the buffer is electricallyconnected to a sense amp electrically connected to the selected memorycell; wherein a number of dummy memory cells from the first plurality ofdummy cells electrically drive the dummy bit line pair when the singledummy word line is driven to a logical high value; wherein a word linethat is electrically connected to the selected memory cell is driven toa logical high value concurrently with the single dummy word line beingdriven to a logical high value.
 4. The electronic device of claim 3wherein the number of dummy memory cells from the first plurality ofdummy cells is determined by a logical block.